====== Bring-Up Guide for the KU060 DUT Board Rev. 1  ======

===== Known Rev.V1 Issues =====
  * J34 and J35 pin Columns A-D are swapped between connectors
    * Practical Impact:
      * FMC1 and FMC2 labels and indicators on the board are swapped
      * FMC1 and FMC2's power domains are merged
      * The order in which the JTAG chain links FMC1 and FMC2 is reversed
      * FMC1 and FMC2's DUT-provided clocks are swapped
      * FPGA-IO-bank mappings for LA[x] and FMC-flag signals are mixed. This must be considered when constraining KU060 FPGA designs and may break timing for some designs.
        * On FMC1, a range of LA[x] signals originates from IO banks dedicated to FMC2 (same for FMC2)
        * trace lengths for the relevant LA[x] signals strongly differs from that of "correctly placed signals"
        * several FMC-flag signals there were supposed to exist on FMC1 now only exist on FMC2 (same for FMC2)
        * All MGTs on FMC1 are assigned to FMC2 (same for FMC2)
        * custom-designed V7-DuT FMC modules that require the specific pin-layout of the V7's FMC-ConfigMon-connector will not be functional.
      * This is a board-design and signal-routing issue, and can not be mitigated without spinning a Rev2 of the KU060 DuT
        *  {{:wiki:ku060_interposer.png?linkonly|A hardware fix (Interposer Card)}} can be obtained from Christian M. Fuchs.
    * Silkscreen description of the FMC JTAG chain bypass jumper settings are swapped.
      * the top (CONNECT) diagram should show vertical connections between pins
      * the bottom (BYPASS) diagram should show horizontal connections
  * G1,G2 MGT clock oscillators seem to be unsuitable for driving MGTs
    * Originally placed on the board because they were in the parts library and considered suitable by the designers, as adding part-entries for our originally desired part would have taken a very long time.
    * The ASEMP 125Mhz MEMS parts placed on the board however turned out to be too unstable and jittery to allow proper MGT operation
    * They can be replaced with the following package and pin compatible part:
      * SI 540BCA125M000Cxxx, the 125M000 indicates an output clock frequency of 125Mhz, if needed, they can be replaced with another clock frequency as desired

===== Operating Modes (Jumper P6) ===== 

==== FuncmonMode ====
Set P6 to Funcmon mode, and the 50Mhz FPGA clock will be obtained from the Teradyne Connectors (i.e. from FuncMon). In this setting a board will not use its own 50Mhz on-board SI clock oscillator.

==== DUTMode (Standalone operation) ====
Set P6 to DUTmode, and the on-board 50Mhz clock oscillator will be connected to the DUT FPGA, and be passed to both FMC modules. It will also be delivered to connected DUT cards via the Teradyne Connectors.

===== Standalone Power-Up Sequence ===== 

==== Jumper P6: CTI/Standalone Operation ====
  - Jumper P6 needs to be set to DUT mode by placing a jumper on pins 1-2 to operate an individual KU060 independently. This makes a board operate using its local clock oscillator, and will not use a clock provided through the Gen4 Backplane.

==== Jumper P5: Configuration Bank Voltage ====

Ultrascale supports the following Config IO settings:
  * **low-range** IO operating at 1.5V and 1.8V with a jumper placed on pins 2-3, using a pin call CFGBVS, as well as
  * **high-range** IO operating at 2.5V and 3.3V with a jumper placed on pins 1-2 for backwards compatibility
Most development boards hardwire this. The KU060 DUT preserve this as configurable option. 

Jumper P5 should short pins 2-3 to drive the configuration IO Bank at 1.8V, if this is desired. 
 
<hi #ff7f27>**The DUT may be damaged if banana CFG_I/O is >1.8V, while P5 is set to "low range"**</hi>

{{:infrastructure:hw:dut_ku060:img_20200814_240733281.jpg?400|}}

==== Jumper P64-67: JTAG Chain Routing ====

Set the JTAG chain bypass jumpers. In below image, the JTAG chain bypasses both FMC connectors and only includes the FPGA. **The JTAG bypass settings for the FMC cards and the silk screen are labeled backwards, the correct setting for bypassing both FMC modules is depicted below.**

{{:infrastructure:hw:dut_ku060:img_20201016_143953123.jpg?400|}}

==== Banana Jacks: Voltage Rail Configuration ====

As example, an image of Gary's initial power setup using only four power supply voltages is shown below: 

{{:infrastructure:hw:dut_ku060:img_20200814_240104076.jpg?400|}}

=== Power Rails: ===
  * GND - all three used (there are three so we never exceed 12A or so of return current on any one, max rating of banana jacks -though probably they work at higher).
  * 0.979V - VCCINT, VCCINTIO, VCCBRAM, MGTAVCC <hi #ff7f27>**(WARNING: SEE BELOW PARAGRAPH)**</hi>
  * 1.2V - MGTAVTT
  * 1.8V - all aux (including VCCADC which is needed for internal voltages and temp over JTAG and MGTVCCAUX) and io's
  * 2.5V - VCC25_BOARD (for local oscillators)
  * N/C - remaining four VREFs and MEZ_PWR33

<hi #ff7f27>**WARNING:**</hi>
Normally at least 5 power rails are required to operate a KU060 FPGA. To simplify the initial test setup, a simpler configuration with only 4 power rails was chosen. In a later setup, a fifth supply set for 1.0V was added where MGTs were powered "correctly". To bring up this DUT with only 4 power rails, Xilinx's recommended procedure for powering unused MGTs were worked around. Gary chose VCCINT, VCCINTIO, VCCBRAM, and MGTAVCC to run from the core voltage rail running at 0.979V (spec-max voltage). This allowed to also drive MGTS within spec on the 1.0V MGTAVC. MGTs can not be expected to work this way, but they are just being brought up and then remain unused in this setup (from experience we know that certain MGTs need to be grounded, and some must be open-drain). 

{{:infrastructure:hw:dut_ku060:img_20200819_101137448_hdr.jpg?400|}}
{{:infrastructure:hw:dut_ku060:img_20200819_091942845_hdr.jpg?400|}}
{{:infrastructure:hw:dut_ku060:img_20200814_240120401_hdr.jpg?400|}}
{{:infrastructure:hw:dut_ku060:img_20200819_092740390_hdr.jpg?400|}}
{{:infrastructure:hw:dut_ku060:img_20200819_091311776_hdr.jpg?400|}}

==== Test Points ====
There are test point to allow convenient test probe access to several signals and voltage rails on the board. This allows a user to determine if voltages are drooping across the top of card; almost any mini-clips or scope probes with grabbers can hook these "loops" pretty securely. They can also be used as the thin gauge 'sense' lines when using power supplies with 'force' and  'sense.' Doing so is recommended for, at least, the core voltage for DUTs outfitted with commercial FPGA parts, and is required for space-use packaged DUTs.

{{:infrastructure:hw:dut_ku060:img_20201016_144133412.jpg?400|}}

